Since the discovery of high temperature superconductivity in copper oxides, there has been a lot of activity in modeling the performance of superconducting interconnects and comparing their performance with normal conductors at low temperatures [1-4]. In contrast, this invention is directed to how high-Tc superconducting tunneling junctions (TJs) and interconnects can be employed to realize a low power, high speed CMOS circuit, which reduces the noise due to simultaneous switching of drivers and provides high densitY communication channels. Although power dissipation and current transients in high speed CMOS cascade circuits have been problematic for almost a decade, few alternative schemes [5,6]have been proposed. High-Tc superconducting-insulator-normal metal (SIN) junctions [7]and superconducting-insulator-superconductor (SIS) junctions with no Josephson currents and high Tc TJs with useful gap voltages have been fabricated. It is possible to develop a process for a multilayer superconducting interconnect system which allows TJs to be fabricated at a relatively small increase in manufacturing cost. By comparison with low-Tc superconductors, the small superconductor energy gap voltages should be very stable and reproducible, in comparison to voltage references and clamps generated from semiconductor diodes like the p-n junction or the Schottky diode. A 0.5.mu.m CMOS technology [8]optimized for 77K operation is assumed for the discussions with this invention.